1. Technical Field
The present invention relates to fabricating integrated circuit structures, and more particularly to a method for electrically interconnecting a plurality of stacked circuit chips.
2. Background Art
Present techniques for improving the performance of semiconductor devices include incorporating multiple integrated circuit chips in the same integrated circuit package to mininize wire path length.
One known technique is to place two or more circuit chips side by side and to electrically connect them using bond wires. This approach introduces lead parasitics that impact performance.
Another known approach is to provide a stacked structure by mounting one circuit chip on top of the other and connecting them using C4 solder ball technology. This approach requires special metallurgy and processing to form the C4 joints.
An example of a technique for arranging stacked circuit chips is described in U.S. Pat. No. 5,532,519 issued Jul. 2, 1996 to Bertin et al. entitled CUBE WIREABILITY ENHANCEMENT WITH CHIP-TO-CHIP ALIGNMENT AND THICKNESS CONTROL. This reference discloses a stacked chip arrangement where protuberances on one chip mate with recesses on another chip for alignment purposes.
Other references relating to stacked circuit chips include:
U.S. Pat. No. 5,661,901 issued Sep. 2, 1997. PA1 U.S. Pat. No. 5,613,033 issued Mar. 18, 1997. PA1 U.S. Pat. No. 5,454,160 issued Oct. 3, 1995. PA1 U.S. Pat. No. 5,356,838 issued Oct. 16, 1994. PA1 U.S. Pat. No. 5,229,647 issued Jul. 20, 1993. PA1 U.S. Pat. No. 5,508,563 issued Apr. 16, 1996. PA1 U.S. Pat. No. 4,996,587 issued Feb. 26, 1991. PA1 U.S. Pat. No. 5,492,223 issued Feb. 20, 1996.